NPU Operators
This section summarizes neural network operators supported by the SyNAP VS6x0/SL16x0 class of NPUs and accompanying software stack. For each operator type, the supported tensor types and execution engines are also documented. Designing networks that maximize the use of operators executed in the NN core will provide the best performance.
Execution Engines
| Acronym | Description |
|---|---|
| NN | Neural Network Engine |
| PPU | Parallel Processing Unit |
| TP | Tensor Processor |
Tensor Types
| Acronym | Description |
|---|---|
| asym-u8 | asymmetric affine uint8 |
| asym-i8 | asymmetric affine int8 |
| pc-sym-i8 | per channel symmetric int8 |
| fp32 | floating point 32 bits |
| fp16 | floating point 16 bits |
| h | half |
| int16 | int16 |
| int32 | int32 |
note
int16 dynamic fixed point convolution is supported by the NN Engine in their multiplication. Other layers follow the tables; if asym-u8 is not available in the NN column, int16 is also not available.
Basic Operations
| Operator | Input | Kernel | Output | NN | TP | PPU |
|---|---|---|---|---|---|---|
| CONV2D | asym-u8 | asym-u8 | asym-u8 | ✔ | ||
| asym-i8 | pc-sym-i8 | asym-i8 | ✔ | ✔ | ||
| fp32 | fp32 | fp32 | ✔ | |||
| fp16 | fp16 | fp16 |